This invention relates to digital to analog (D/A) conversion circuits. Some prior art D/A circuits may be found in section 8 of the 1978 Linear Databook by National Semiconductor, for example. The type of D/A circuits with which we are here concerned include R-2R resistive ladders. Basically, these ladders are comprised of a plurality of resistors which are interconnected as a series of N stages. Each stage contains the serial leg which connects to the next stage, and a parallel output leg which is coupled via a transistorized switch to a pair of conductive output buses. This serial leg contains resistor R while the parallel output leg contains resistors 2R.
Ideally, the resistance of each of the resistors in the ladder network are identical, and the resistance through each of the switches is zero. In actual practice, however, the transistor switches always have some resistance associated with them. This is because the resistance through a conducting transistor is proportional to the transistors physical size; and to reduce that resistance to zero would cause the transistors to occupy an unreasonably large amount of chip space.
One prior art solution to this problem was to scale the resistance of each of the switches such that they differed from each other by powers of two. The switch having the smallest resistance was coupled to the output leg of the most significant stage, whereas the switch having the largest resistance was coupled to the output leg of the least significant stage. With this arrangement, it can be shown that current divides equally within each of the stages.
This solution, however, is unattractive when the D/A converter circuit has a large number of stages, such as ten or more. In that case, those switches connected to the least significant stages still must necessarily be so small that they are difficult to fabricate. Therefore, another solution to the problem of compensating for the switches resistance is desired.
Accordingly, it is a primary object of the invention to provide a digital to analog conversion circuit which compensates for inaccuracies caused by switch resistance within the circuit while simultaneously permitting the size of the switches to stay within a reasonably narrow range.